In strained silicon CMOS, the carrier transport properties are enhanced by the biaxial tensile strain in the strained silicon layer on relaxed SiGe. Strained silicon MOSFETs have been demonstrated on SiGe-on-insulator (SGOI) substrates with the combination of the high mobility in strained silicon and advantages of SOI structures in sub-100 nm devices. K. Rim et al., Strained Si for sub-100 nm MOSFETs, Proceedings of the 3rd International Conference on SiGe Epitaxy and Heterostructures, Sante Fe, New Mexico, Mar. 9–12, 2002, p125.
Methods to fabricate SiGe-on-insulator substrate have been reported by the MIT group and IBM. Transfer of SiGe onto insulator substrate was achieved by Smart-Cut technique through hydrogen implantation and annealing. M. Bruel et al., Smart-Cut: A New Silicon On Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding, Jpn. J. Appl. Phys., Vol. 36, 1636 (1997); Z.-Y. Cheng et al., SiGe-on insulator (SGOI): Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation, 2001 IEEE International SOI Conference Proceedings p 13; Z. Cheng et al., Relaxed Silicon-Germanium on Insulator Substrate by Layer Transfer, Journal of Electronics Materials, Vol. 30, No. 12, 2001, L37; and G. Taraschi et al., Relaxed SiGe on Insulator Fabricated via Wafer Bonding and Layer Transfer: Etch-back and Smart-Cut Alternatives, Electrochemical Society Proceedings Vol. 2001–3, p27; and L.-J. Huang et al., Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding, 2001 Symposium on VLSI Technology Digest of Technical Papers, p 57.
In the prior art, a thick layer SiGe is deposited on a silicon substrate, which includes a graded SiGe buffer layer and a relaxed SiGe layer having a constant germanium concentration. Following surface planarization, as by CMP, hydrogen is implanted into the SiGe layer to facilitate wafer splitting. The Si/SiGe wafer is then bonded to a oxidized silicon substrate. The SiGe-on-oxide is separated from the rest of the couplet by thermal annealing, wherein splitting occurs along hydrogen-implantation-induced microcracks, which parallel the bonding interface.
A technique to form a SiGe-free strained silicon on insulator substrates has been also reported by T. A. Langdo et al., Preparation of Novel SiGe-Free Strained Si on Insulator Substrates, 2002 IEEE International SOI Conference Proceedings, October 2001, p211. This technique is similar to previously described techniques, except that a thin layer of epitaxial silicon is deposited on the SiGe layer before wafer bonding. After bonding and wafer splitting, the SiGe layer is removed by oxidation and HF etching, enabling the formation of very thin and uniform strained silicon on oxide surface.
The above techniques all involve thicker SiGe layer, and require one or two elaborate CMP process. The relaxation of SiGe on borophosphorosilicate glass (BPSG) after film transfer and island formation. H. Yin et al., Strain relaxation of SiGe islands on compliant oxide, Journal of Applied Physics, 91, 2002, 9718.